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THC63LVD824a _rev1.20_e copyright?2014 thine electronics, inc. 1/14 thine electronics, inc. THC63LVD824a single(112mhz)/dual(170mhz) link lvds receiver for xga/ sxga/sxga+/uxga general description the THC63LVD824a receiver is designed to support single link transmission between host and flat panel display up to sxga resolutions and dual link trans- mission between host and flat panel display up to uxga resolutions. the THC63LVD824a converts the lvds data streams back into 48bits of cmos/ttl data with falling edge or rising edge clock for convenient with a variety of lcd panel controllers. in single link, data transmit clock frequency of 112mhz, 48bits of rgb data are transmitted at an effective rate of 784mbps per lvds channel. using a 112mhz clock, the data throughput is 392mbytes per second. in dual link, data transmit clock frequency of 85mhz, 48bits of rgb data are transmitted at an effective rate of 595mbps per lvds channel. using a 85mhz clock, the data throughput is 595mbytes per second. features ? wide dot clock range: 25-170mhz suited for vga, svga, xga, sxga, sxga+ and uxga ? pll requires no external components ? supports single link up to 112mhz dot clock for sxga ? supports dual link up to 170mhz dot clock for uxga ? 50% output clock duty cycle ? ttl clock edge programmable ? ttl output driverbility se lectable for lower emi ? power down mode ? low power single 3.3v cmos design ? 100pin tqfp ? thc63lvdf84b compatible ? pin compatible with THC63LVD824 block diagram serial to parallel pll serial to parallel pll 28 28 demux ra1 +/- rb1 +/- rc1 +/- rd1 +/- rclk1 +/- ra2 +/- rb2 +/- rc2 +/- rd2 +/- r/f /pdwn (25 to 112mhz) rclk2 +/- (25 to 85mhz) 1st link 8 8 8 8 8 8 red1 green1 blue1 hsync vsync de red2 green2 blue2 receiver clock out (12.5 to 85mhz) 1st data 2nd data cmos/ttl output 2nd link lvds input
copyright?2014 thine electronics, inc. 2/14 thine electronics, inc. THC63LVD824a _rev1.20_e pin out lvds gnd ra1- ra1+ rb1- rb1+ lvds vcc rc1- rc1+ rclk1- rclk1+ rd1- rd1+ lvds gnd ra2- ra2+ rb2- rb2+ lvds vcc rc2- rc2+ rclk2- rclk2+ rd2- rd2+ lvds gnd 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 r15 gnd vcc r14 r13 r12 r11 r10 gnd vcc clkout b27 b26 b25 b24 b23 gnd vcc b22 b21 b20 g27 gnd vcc g26 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 pll gnd pll vcc gnd /pdwn mode0 mode1 gnd r/f drvsel r20 r21 r22 r23 r24 vcc gnd r25 r26 r27 g20 g21 g22 g23 g24 g25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 de vsync hsync b17 b16 gnd vcc b15 b14 b13 b12 b11 b10 g17 g16 g15 g14 g13 gnd vcc g12 g11 g10 r17 r16 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
copyright?2014 thine electronics, inc. 3/14 thine electronics, inc. THC63LVD824a _rev1.20_e pin description pin name pin # type description ra1+, ra1- 78, 77 lvds in the 1st link. the 1st pixel input data when dual link. rb1+, rb1- 80, 79 lvds in rc1+, rc1- 83, 82 lvds in rd1+, rd1- 87, 86 lvds in rclk1+, rclk1- 85, 84 lvds in lvds clock input for 1st link. ra2+, ra2- 90, 89 lvds in the 2nd link. these pins are disabled when single link. rb2+, rb2- 92, 91 lvds in rc2+, rc2- 95, 94 lvds in rd2+, rd2- 99, 98 lvds in rclk2+, rclk2- 97, 96 lvds in lvds clock input for 2nd link. r17 ~ r10 52, 51, 50, 47, 46, 45, 44, 43 out the 1st pixel data outputs. g17 ~ g10 62, 61, 60, 59, 58, 55, 54, 53 out b17 ~ b10 72, 71, 68, 67, 66, 65, 64, 63 out r27 ~ r20 19, 18, 17, 14, 13, 12, 11, 10 out the 2nd pixel data outputs. g27 ~ g20 29, 26, 25, 24, 23, 22, 21, 20 out b27 ~ b20 39, 38, 37, 36, 35, 32, 31, 30 out de 75 out data enable output. vsync 74 out vsync output. hsync 73 out hsync output. clkout 40 out clock output. drvsel 9 in r/f 8 in output clock triggering edge select. h: rising edge, l: falling edge. mode1, mode0 6, 5 in /pdwn 4 in h: normal operation, l: power down (all outputs are pulled to ground) vcc 15, 27, 33, 41, 48, 56, 69 power power supply pins for ttl outputs and digital circuitry. gnd 3, 7, 16, 28, 34, 42, 49, 57, 70 ground ground pins for ttl outputs and digital circuitry. lvds vcc 81,93 power power supply pins for lvds inputs. lvds gnd 76, 88, 100 ground ground pins for lvds inputs. output driverbility select. drvsel clock data h 8ma 4ma l 4ma 2ma pixel data mode. mode1 mode0 mode l l dual link (dual-in/dual-out) l h single link(single-in/dual-out) other not available
copyright?2014 thine electronics, inc. 4/14 thine electronics, inc. THC63LVD824a _rev1.20_e absolute maximum ratings 1 electrical characteristics cmos/ttl dc specifications v cc = 3.0v ~ 3.6v, ta = -10 ~ +70 lvds receiver dc specifications v cc = 3.0v ~ 3.6v, ta = -10 ~ +70 pll vcc 2 power power supply pin for pll circuitry. pll gnd 1 ground ground pin for pll circuitry. supply voltage (v cc ) -0.3v ~ +4.0v cmos/ttl input voltage -0.3v ~ (v cc + 0.3v) ( Q 4.0v) cmos/ttl output voltage -0.3v ~ (v cc + 0.3v) ( Q 4.0v) lvds receiver input voltage -0.3v ~ (v cc + 0.3v) ( Q 4.0v) output current -15ma ~ 15ma junction temperature +125 storage temperature range -55 ~ +125 maximum power dissipation @+25 1.7w 1. ?absolute maximum ratings? are those valued beyond which the safety of the device can not be guaranteed. they are not meant to imply that th e device should be operated at these limits. the tables of ?electrical characteristics? specify conditions for device operation. symbol parameter conditions min. typ. max. units v ih high level input voltage 2.0 v cc v v il low level input voltage gnd 0.8 v v oh high level output voltage i oh = -2ma, -4ma (data) i oh = -4ma, -8ma (clock) 2.4 v v ol low level output voltage i ol = 2ma, 4ma (data) i ol = 4ma, 8ma (clock) 0.4 v i inc input current a symbol parameter conditions min. typ. max. units v th differential input high threshold v ic = 1.2v 100 mv v tl differential input low threshold v ic = 1.2v -100 mv i inl input current v in = 2.4v / 0v v cc = 3.6v a pin name pin # type description c c c c c c 0v v in v cc ? 10 c c 20
copyright?2014 thine electronics, inc. 5/14 thine electronics, inc. THC63LVD824a _rev1.20_e switching characteristics v cc = 3.0v ~ 3.6v, ta = -10 ~ +70 symbol parameter min. typ. max. units t rcp clkout period dual-in / dual-out 11.76 t rcip 40.0 ns single-in / dual-out 17.85 2t rcip 80.0 ns t rch clkout high time ns t rcl cklout low time ns t rs ttl data setup to clkout 0.3t rcp -0.5 ns t rh ttl data hold from cklout 0.3t rcp -0.5 ns t tlh ttl low to high transition time 2.5 4.0 ns t thl ttl high to low transition time 2.5 4.0 ns t sk receiver skew margin clkin=85mhz -0.40 +0.40 ns clkin=112mhz -0.25 +0.25 ns t rip1 input data position0 -t sk 0.0 +t sk ns t rip0 input data position1 ns t rip6 input data position2 ns t rip5 input data position3 ns t rip4 input data position4 ns t rip3 input data position5 ns t rip2 input data position6 ns t rpll phase lock loop set 10.0 ms t rcip clkin period 8.92 40.0 ns t ck12 skew time between rclk1 and rclk2 ns c c t rcp 2 ---------- - t rcp 2 ---------- - t rcip 7 ------------ -t sk ? t rcip 7 ------------ - t rcip 7 ------------ -t sk + 2 t rcip 7 ------------ -t sk ?2 t rcip 7 ------------ -2 t rcip 7 ------------ -t sk + 3 t rcip 7 ------------ -t sk ?3 t rcip 7 ------------ -3 t rcip 7 ------------ -t sk + 4 t rcip 7 ------------ -t sk ?4 t rcip 7 ------------ -4 t rcip 7 ------------ -t sk + 5 t rcip 7 ------------ -t sk ?5 t rcip 7 ------------ -5 t rcip 7 ------------ -t sk + 6 t rcip 7 ------------ -t sk ?6 t rcip 7 ------------ -6 t rcip 7 ------------ -t sk + 0.3t rcip supply current v cc = 3.0v ~ 3.6v, ta = -10 ~ +70 symbol parameter condition(*) typ. max. units i rccw receiver supply current (worst case pattern) f clkout = 85mhz mode<1:0>=ll cl=8pf, vcc=3.6v 225 ma i rccs receiver power down supply current /pdwn = l 10 a c c
copyright?2014 thine electronics, inc. 6/14 thine electronics, inc. THC63LVD824a _rev1.20_e ac timing diagrams ttl outputs phase lock loop set time vcc 3.0v 2.0v 2.0v t rpll rclkx+/- /pdwn clkout vcc/2 r/f = l r/f = h t rcp t rs t rh t rch t rcl clkout vcc/2 vcc/2 vcc/2 vcc/2 rxn gxn bxn x = 1,2 n = 0~7 8pf ttl output ttl output load 20% 80% 20% 80% t tlh t thl
copyright?2014 thine electronics, inc. 7/14 thine electronics, inc. THC63LVD824a _rev1.20_e pixel map table for single/dual link tft panel data lsb 24bit 18bit 824a ttloutputpin 1st pixel data r10 - msb r11 r12 r13 r14 r15 r16 r17 - r10 r11 r12 r13 r14 r15 lsb msb g11 g12 g13 g14 g15 g16 g17 - g10 g11 g12 g13 g14 g15 g10 - lsb msb b11 b12 b13 b14 b15 b16 b17 - b10 b11 b12 b13 b14 b15 b10 - r10 r11 r12 r13 r14 r15 r16 r17 g11 g12 g13 g14 g15 g16 g17 g10 b11 b12 b13 b14 b15 b16 b17 b10 tft panel data lsb 24bit 18bit 824a ttloutputpin 2nd pixel data r20 - msb r21 r22 r23 r24 r25 r26 r27 - r20 r21 r22 r23 r24 r25 lsb msb g21 g22 g23 g24 g25 g26 g27 - g20 g21 g22 g23 g24 g25 g20 - lsb msb b21 b22 b23 b24 b25 b26 b27 - b20 b21 b22 b23 b24 b25 b20 - r20 r21 r22 r23 r24 r25 r26 r27 g21 g22 g23 g24 g25 g26 g27 g20 b21 b22 b23 b24 b25 b26 b27 b20
copyright?2014 thine electronics, inc. 8/14 thine electronics, inc. THC63LVD824a _rev1.20_e tft panel (1280 x 1024) #1 #2 #1280 #1279 hsync de clkout r1x/g1x/b1x r2x/g2x/b2x #1 #2 #3 #4 #5 #6 #8 #1279 #1280 #1277 #1278 1275 1276 #7 n = 0~7 824a ttl data output timing for single/dual link example : sxga(1280 x 1024)
copyright?2014 thine electronics, inc. 9/14 thine electronics, inc. THC63LVD824a _rev1.20_e v diff = 0v ryx+/- ac timing diagrams lvds inputs ryx6 ryx5 ryx4 ryx3 ryx2 ryx1 ryx0 ryx6 ryx5 ryx4 ryx3 ryx2 ryx1 v diff = 0v t rip2 t rip3 t rip4 t rip5 t rip6 t rip0 t rip1 t rcip rclkx+ x = 1,2 y = a,b,c,d v diff = 0v t ck12 rclk1+ v diff = 0v rclk2+ note: v diff = (ryx+) - (ryx-), (rclkx+) - (rclkx-)
copyright?2014 thine electronics, inc. 10/14 thine electronics, inc. THC63LVD824a _rev1.20_e lvds data inputs timing diagrams in single link ra1+/- r26? r25? r24? r23? r22? g12 r17 r16 r15 r14 r13 r12 g22?? rb1+/- g27? g26? g25? g24? g23? b13 b12 g17 g16 g15 g14 g13 b23?? rc1+/- hsync? b27? b26? b25? b24? de vsync hsync b17 b16 b15 b14 de?? rd1+/- b20? g21? g20? r21? r20? x b11 b10 g11 g10 r11 r10 x?? rclk1+ previous cycle current cycle (2nd pixel data) (1st pixel data)
copyright?2014 thine electronics, inc. 11/14 thine electronics, inc. THC63LVD824a _rev1.20_e lvds data inputs timing diagrams in dual link ra1+/- r16? r15? r14? r13? r12? g12 r17 r16 r15 r14 r13 r12 g12?? rb1+/- g17? g16? g15? g14? g13? b13 b12 g17 g16 g15 g14 g13 b13?? rc1+/- hsync? b17? b16? b15? b14? de vsync hsync b17 b16 b15 b14 de?? rd1+/- b10? g11? g10? r11? r10? x b11 b10 g11 g10 r11 r10 x?? ra2+/- r26? r25? r24? r23? r22? g22 r27 r26 r25 r24 r23 r22 g22?? rb2+/- g27? g26? g25? g24? g23? b23 b22 g27 g26 g25 g24 g23 b23?? rc2+/- b27? b26? b25? b24? b27 b26 b25 b24 rd2+/- b20? g21? g20? r21? r20? x b21 b20 g21 g20 r21 r20 x?? rclk1+ rclk2+ x?? xxx x? previous cycle current cycle
copyright?2014 thine electronics, inc. 12/14 thine electronics, inc. THC63LVD824a _rev1.20_e note 1)power on sequence power on lvds-tx after THC63LVD824a. if it is not avoidable, please contact to mspsupport@thine.co.jp (for fae mailing list) 2)cable connection and disconnection don't connect and disconnect the lvds cable , when the power is supplied to the system. 3)gnd connection connect the each gnd of the pcb wh ich lvds-tx and THC63LVD824a on it. it is better for emi reduction to place gnd cable as close to lvds cable as possible. 4)multi drop connection multi drop connection is not recommended. 5)asynchronous use asynchronous use such as followin g systems are not recommended. if it is not avoidable, please contact to mspsupport@thine.co.jp (for fae mailing list) THC63LVD824a lvds-tx THC63LVD824a tclk+ tclk- THC63LVD824a THC63LVD824a lvds-tx lvds-tx ic clkout clkout data data ic tclk+ tclk- tclk+ tclk- clkout data data THC63LVD824a THC63LVD824a ic tclk+ tclk- tclk+ tclk- clkout data data ic
copyright?2014 thine electronics, inc. 13/14 thine electronics, inc. THC63LVD824a _rev1.20_e package 76 100 50 26 index pin no.1 25 51 75 0.20 0.5typ 1.2max units:mm 14.0sq typ 16.0sq typ
copyright?2014 thine electronics, inc. 14/14 thine electronics, inc. THC63LVD824a _rev1.20_e notices and requests 1. the product specifications descri bed in this material are subjec t to change without prior notice. 2. the circuit diagrams described in this material are examples of the application which may not always apply to the customer's design. we are not responsible for possi ble errors and omissions in this material. please note if errors or omissions should be fo und in this material, we may not be able to correct them immediately. 3. this material contains our copyright, know-how or other proprietary. c opying or disclosing to third parties the contents of this material without our prior permission is prohibited. 4. note that if infringement of any third part y's industrial ownership s hould occur by using this product, we will be exempted fro m the responsibility unless it di rectly relates to the production process or functions of the product. 5. this product is presumed to be used for general electric equi pment, not for the applications which require very high reliability (including medical equipment direct ly concerning people's life, aerospace equipment, or nuclear control eq uipment). also, when using this product for the equipment concerned with the control and safety of the transportation means, the traffic signal equipment, or various types of safety equipment, please do it after ap plying appropriate measures to the product. 6. despite our utmost efforts to im prove the quality and re liability of the product, faults will occur with a certain small pr obability, which is inevitable to a semi-conductor product. therefore, you are encouraged to have sufficiently redundant or error preventive design applied to the use of the product so as not to have our produc t cause any social or public damage. 7. please note that this product is not designed to be radiation-proof. 8. customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under the foreign ex change and foreign trade control law. thine electronics, inc. e-mail : sales@thine.co.jp

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